A DRAM is a memory element which typically holds and supplies information in a microprocessor based computer system. The microprocessor based system may be a general purpose computer system or may be an application-specific integrated circuit (ASIC) or a system-level integrated circuit (SLIC) which is fabricated to perform a specific function. The system uses a system clock which provides pulses at a predetermined rate. The system clock pulses coordinate many system functions and operations, including generally synchronizing the timing of the DRAM operations with those of the microprocessor. The DRAM delivers information to, and receives information from the microprocessor, via electrical conductors over a system bus. The information stored in the DRAM is used by the microprocessor for computation and control of other peripheral components typically associated with the microprocessor-based system.
The typical DRAM comprises a plurality of DRAM segments and control logic for controlling the DRAM segments. The typical DRAM segment is formed by thousands of individual memory cells arranged in a matrix-like configuration. Each DRAM cell includes a capacitor which is electrically charged in a "write" operation. The electrical charge establishes a voltage on the capacitor, and the level of the voltage represents data. A higher voltage level represents a "1" data bit, while a lower voltage level represents a "0" data bit, or vice versa. The voltage level on the capacitor is sensed during a "read" operation.
The cells of the matrix are addressed by signals supplied on a word line and signals read from selected bit lines or written on selected bit lines. The word lines extend along horizontal rows of cells and intersect vertical columns of cells in the matrix. The bit lines extend along vertical columns of cells and intersect horizontal rows of cells in the matrix. In concept, by energizing a selected word line and reading or writing only on selected bit lines, individual cells at the intersections of the selected word and bit lines are written or read. In this manner, unique memory "addresses" represent specific word line and bit line combinations which access the information located at the cells identified by the address. Memory cell addresses are used by the microprocessor in organizing memory information.
The control logic interacts with the microprocessor and effectively performs the read and write operations on the DRAM memory cells. The control logic receives control signals from the microprocessor requesting a read or write operation, and address signals indicating the memory cell addresses where the read or write operation is to be performed. The control logic then produces the necessary control and address signals to carry out the read or write operation on the addressed memory cells. For a write operation, the microprocessor also provides the data to be stored in the addressed memory cells. For a read operation the data obtained from the addressed DRAM cells is supplied to the microprocessor.
In order for the DRAM control logic to use the information supplied by the microprocessor, which may only be available for a short period of time, the control logic temporarily stores the information in temporary "input" registers. The DRAM control logic recognizes when the information is available and produces a "latch control signal" that secures or "latches" the information into the temporary registers. Thus, the latch control signal produced by the DRAM control logic stores the information located on the address and data buses into the temporary DRAM registers.
Ideally, the DRAM control logic should latch the information into the temporary registers with the same system clock pulse used by the microprocessor to place the data and address information on the system bus. However, the signals on the system bus must propagate through the microprocessor logic and along the system bus until they appear at the DRAM. Because of signal propagation effects, the information on the bus usually is not stabilized until after the system clock pulse has passed. Therefore the DRAM control logic cannot use the same system clock pulse and must create a delayed latch control signal to store or latch the information into the registers once the information has stabilized.
Consequently, the DRAM control logic must generate a number of DRAM control signals internally, independently of the system clock but not synchronized with the system clock pulses. However the DRAM control signals must occur within predetermined time limits set by the system clock, in order to interface and coordinate with the system operation in a time-efficient manner. The timing characteristics of the DRAM control signals are dependent on the characteristics of the DRAM which may vary from one DRAM to another or may vary according to the different types of SLICs into which the DRAM is integrated.
Delay circuits are typically used in the DRAM control logic to create the latch control signal. Otherwise, the DRAM control logic would be forced to use the next system clock pulse as a control signal to store the microprocessor-created information into the temporary registers. Waiting for another system clock pulse significantly slows the speed of the memory, slows the performance of the system microprocessor, and is thus undesirable.
After storing the information in the temporary registers using the DRAM latch control signal, the DRAM control logic uses the stored information to read or write the memory cells during the next system clock cycle. To read memory cells, a segment enable control signal is delivered to a segment of the DRAM array containing the particular cells. Additionally, address signals indicating the particular word and bit lines to be activated are also delivered to the DRAM segment. The energized word line signal causes a transistor in the memory cells of that row to become conductive. With the transistors in a conductive state, the voltages existing on the memory cell capacitors are placed on the bit lines associated with that DRAM segment. Control signals are conducted to enable sense amps of the selected bit lines and sense the voltage on the bit line connected to the particular memory cell and complete the read process.
The sense amps compare a bit line voltage to a threshold voltage and determine whether the bit line voltage is higher or lower than the threshold voltage. If the voltage is higher than the threshold voltage, then the information stored in the memory cell represents a 1 data bit. Similarly, if the voltage is lower than the threshold voltage then the information stored in the memory cell represents a 0 data bit. The opposite relationship may also be employed to establish 1 data bits and 0 data bits. Alternatively, two capacitors may be used to store relatively different charges to represent the data bits. Instead of comparing the charge of one capacitor to a threshold voltage, the two stored charges are compared to each other. Comparing the relative voltage relationship yields the 1 and 0 data bit information stored in the memory cell. The two differential capacitor DRAM memory cell structure is discussed more completely in co-pending application titled "Embedded DRAM with Noise-Protected Differential Capacitor Memory Cells," Ser. No. 09/052,279, which was filed on Mar. 30, 1998.
Generally, to accomplish sensing, the DRAM control logic delivers a sense amp enable control signal to the sense amps which persists while the sense amps are operative. The DRAM control logic negates the sense amp enable control signal when no sensing is required.
Once the sense amps have produced data bit signals based on the memory cell signals, the data is stored in a temporary "output" register in the DRAM control logic until the microprocessor is ready to accept the data, usually in the next system clock cycle after the data is available. The DRAM control logic produces a latch control signal to store the data in the temporary "output" registers in a similar manner to the creation of the latch control signal to store incoming data in the "input" temporary registers.
Additionally, the DRAM control logic produces an output enable control signal to enable the delivery of the signals from the output registers. The output enable control signal is conducted to the microprocessor after the signals from the output registers have been placed on the system data bus. Once the microprocessor receives the output enable signal, it recognizes that the data is present on the system data bus and is available to be used by the microprocessor.
Besides the control signals for the read and write operations, the DRAM control logic also produces control signals to perform other typical DRAM operations, e.g., "memory segment enable," "precharge" and "refresh." The memory segment enable operation involves the conduction of a control signal to the proper memory segment to activate that segment for either a read or write operation.
The precharge operation typically occurs before any voltages from the memory cells are applied to the bit lines. During the precharge operation, a voltage is applied to all the bit lines to charge each bit line to a point approximately midway between an expected high voltage and an expected low voltage from the memory cell capacitors. During a subsequent read or write operation, the charge on the capacitor modifies the charge on the bit line. Since the bit line has been partially charged to the midpoint between the high and low values, the time it takes for the connected memory cell capacitor to bring the bit line charge to the level of the memory cell capacitor is reduced, thus increasing the performance of the DRAM. Moreover, the time it takes to modify the charge on the precharged bit line is substantially less than the worst-case time for charging a non-precharged bit line to a high voltage level. Therefore, during a read operation the sense amps can effectively begin sensing the bit lines sooner, and during a write operation, the time allotted to charging the memory cell capacitor is reduced. Additionally, since the precharge operation can take place simultaneously with other internal operations, for example during decoding of the memory address, the overall read or write operation time is reduced.
The control logic also produces refresh control signals to refresh the charge on the memory cell capacitors since the charges are not "permanent" and dissipate after a relatively short period of time, typically on the order of a few milliseconds. Thus the DRAM control logic conducts a refresh operation which recharges the memory cell capacitors and maintains the integrity of the stored information. The refresh process typically involves reading the information stored in the memory cells, temporarily storing the information in registers, and then writing the information back into the memory cells. Read operations are destructive because they diminish the stored charge on the memory cell and for this reason, a "write-back" operation is typically performed to recharge the read memory cell. The DRAM control logic continuously refreshes the memory by performing read-write back operations on different portions of memory, before the charges have dissipated and data is lost on any portion. No data signals are required to perform the read-write back operations, since the data signals read are the same ones written back, so the DRAM control logic can perform the refresh operation autonomously. The DRAM control logic is programmed to refresh separate portions of memory during each system clock cycle. The order in which memory cells are refreshed is not overly important, as long as each memory cell is refreshed before the memory cell charge has decreased below necessary threshold levels and the data is lost. Typical DRAM memory cells require refreshing every one or two milliseconds, and the DRAM control logic assures that all the memory cells in the segment are refreshed within this time frame.
The control signals delivered by the DRAM logic are usually voltage pulses or "strobes," which remain asserted for the duration of the operation. When a control signal strobe decreases to a relatively lower level, the operation initiated by the control signal terminates. Other DRAM logic control signals may be active at a low voltage level, and a high voltage is consequently present during periods of non-operation. In either case, it is important that the strobes remain asserted until the operation has had sufficient time to complete its task, otherwise improper data storage or recovery or unreliable operation of the DRAM may result.
During the precharge operation, for example, the predetermined time period must be sufficiently long to allow all the bit lines to completely precharge to the midpoint level. The typical minimum or shortest time period for a precharge operation is defined by the time it takes for a signal to propagate along the length of a bit line with the greatest propagation time. Usually, the bit line with the highest resistence or greatest length or both has the greatest propagation time, and it determines the minimum precharge time period for a given memory segment. The DRAM control Logic should assert the precharge control signal for a time period which is equal to the minimum precharge time period. Otherwise, the DRAM control logic may assert the precharge control signal for a time period which is too short, causing premature termination of the precharge operation and resulting in inadequately precharged bit lines. Alternatively, the DRAM control logic may assert the precharge control signal for a time period which is too long and therefore waste time which might be used to perform other memory functions, thereby diminishing the performance of the memory.
The minimum time periods associated with satisfactory completion of the read, write and refresh operations are also dependent upon the time it takes for signals to propagate along the word and bit lines. The speed of the memory can be enhanced by consuming no more than the minimum signal propagation time for the read, write and refresh operations. The actual signal propagation times for each bit and word line depend on the characteristics of the bit or word line conductors, and these characteristics vary somewhat in different chips based on the manufacturing process.
The complex manufacturing process typically causes unforseen and usually uncontrollable slight variations from chips in different manufacturing lots, often resulting in propagation time variations.
Additionally, the minimum operating temperature of the chip also influences the time required to complete the DRAM operations. Typically, the operating temperature of the bit and word line conductors fluctuates during operation because of current conduction and other environmental conditions. As the temperature increases in the semi-conductors, the resistance increases and the current conduction generally decreases. As current conduction changes, signal propagation times also change. Thus, for a given voltage, operating temperatures influence the minimum time required for satisfactory completion of each operation and the optimal propagation times.
Similarly, the operating voltages applied to the word and bit lines may vary during the operation of the DRAM module and these fluctuations also affect the required minimum time periods for each DRAM operation. The primary cause of the voltage variations is due to component variations in the power supply. When the voltages applied to the bit or word lines increase, current conduction generally increases which causes signal propagation time to decrease. However, when the applied voltage decreases, the current conduction also decreases which slows signal propagation and increases the minimum time periods for each operation.
The typical approach to accounting for these process, temperature and voltage variations is to assert the DRAM control signals for time periods sufficient to accommodate worst case conditions. However, worst case timing is usually longer than necessary, and time is wasted during normal operations in accounting for worst case occasions. The performance or speed of the DRAM is slowed, or the system performance is reduced because more system clock cycles will be required to accomplish the DRAM operations.
A partial solution to these worst case variables involves a determination of the propagation times. A redundant word line is inserted in the DRAM segment, and a signal is propagated through the redundant word line at the beginning of a given memory operation. The propagation of the signal is timed by the DRAM control logic, and the additional time required for propagation is added to the minimum time periods for each operation. Once accounted for in this manner, the control signals remain asserted for a time period based on a best-case minimum time period combined with the calculated delay.
Although the additional redundant word line provides some compensation for variations in propagation times, the compensation calculation itself requires additional time and although better than worst case conditions, still may not be optimum. Furthermore, the redundant word line compensation technique will not quickly provide control timing information for all the control signals supplied by the DRAM control logic.
It is with respect to these and other considerations relating to creating DRAM logic circuits that the present invention has evolved.